The invention relates to integrated circuits and more particularly to integrated circuits of the very large scale integration (VSLI) type. Integrated circuits are also known as chips. At present, VLSI chips are small, substantially square semiconductor plates, measuring about one centimeter on a side and having a thickness of less than one millimeter. The active face of a chip incorporates the circuits which are integrated in the small plate and carry the input/output pads. The opposite face of a chip is called the chip back. Because of the very large scale integration, the active face ordinarily contains on the order of 500 pads, and is subject in operation to a high heat density which must be dissipated. For example, a VSLI chip of the N-MOS type (that is, field-effect transistors of the metal-oxide- semiconductor type, or FET-MOS) can dissipate on the order of four watts.
Generally, several chips are interconnected by mounting them on a printed circuit board. Mounting is performed by two well known methods. The most current method comprises encapsulating each chip in a package and soldering the terminals of the package on the corresponding zones on a printed circuit board. The packages afford good mechanical protection and are easily assembled on a board, but they have the disadvantage of being very bulky, and the number of them that can be accommodated on a board is limited. The second method overcomes this disadvantage by connecting each chip directly to the board. This technique is currently known as "micropackaging".
To facilitate handling of bare chips before they are mounted on a card or board, a method presently known as tape-automated bonding (TAB) comprises disposing the integrated circuits on a flexible carrier tape known as TAB tape. Each chip is provided with leads adapted to be supported on the edges of a window formed into the tape. The leads of each chip are cut off on the inside of the window to separate the chip from the tape and the leads are then soldered to corresponding zones of a printed circuit board in an output lead bonding (OLB) operation.
In a standard manner, the backs of the chips rest on the printed circuit board, and their leads which are pre-bent come into contact with contact zones of the board, to which they are soldered using an OLB soldering tool. In this case, the heat generated is dissipated via the board.
In another mode of manufacture, called reverse TAB or FLIP-TAB, the tape is presented so that the active faces of the chips are located facing the board. The leads of the chips are soldered to the zones on the card or board without being bent beforehand. A heat dissipating element is applied to the back of each chip.
The standard package for a VLSI chip is a pin-grid array package. In this package, the back of the chip rests on the bottom of a cavity made on one face of a multilayer integrated circuit board and surrounded by several rows of pins at right angles to the board. The edges of the cavity are arranged in steps, provided with zones for connection to the corresponding pads of the chip. This connection is done by wire bonding. The chip back is in contact with a heat dissipating element that emerges from the other face of the board so that it can be connected to a cooling device such as a heat sink. Mounting of the package on a board is preferably done by a zero insertion force (ZIF) connector. The pins are introduced into the connector without force, and are then secured in the contact elements of the connector.
In practice, the method of mounting a chip on a board via a pin-grid array package has many disadvantages. The printed circuit board is a complex, costly element, and highly susceptible to defects. The conductor elements of printed circuits are arranged on several planes, for example six, that are interconnected between adjacent planes by vias. These conductor elements are quite narrow, to accommodate the high density required by the great number of pads of the chip. The relative disposition of these elements and the corresponding vias must accordingly be very precise, to assure correct bonding at all points. In practice, this condition is difficult to meet, and it increases the cost of a board. Moreover, connecting the pads of the chip to the zones of the package cavity is presently done by soldering very thin wires, typically of gold or aluminum. Taking into account the high density of the pads and the distribution of the zones in steps, the automation of wire bonding is complicated and delicate.
Briefly, bonding of a pad of a chip to a corresponding pin of the package typically involves twice soldering the wire connecting the pad to the corresponding zone of the package; thin, narrow conductors realized as printed circuits in the multilayer board; vias for interconnecting the conductor elements; and finally, soldering the last conductor element to the pin. The package equipped with the chip thus contains a high number of connection points, which affects the dependability of the overall package and increases its cost. Finally, the package is mounted on a ZIF connector of a printed circuit board. This connector has the advantage of being dependable and of furnishing an easily moved connection, but it has the disadvantage of being bulky and expensive.
Using the TAB technique for making a package has already been proposed in French Patent No. 2 456 390. This patent exploits the essential feature of TAB, which is to have each chip provided with its set of leads supported by a tape. According to this patent, the cut-off ends of the leads of a TAB tape comprise the output terminals of a package that is formed simply by sheathing the chip and the adjacent portions of its leads in an electrical insulation resin. The resin also keeps in place a heat dissipating element applied to the chip back. Each lead is of only slight thickness in the vicinity of the chip, and its thickness is great beyond the chip. The slight thickness lends the leads the requisite flexibility for uniform and reliable soldering of all the leads to the pads of the chip, while the great thickness of the leads notably increases the rigidity of the resin of the package and furnishes the desired rigidity for the output terminals of the package.
This TAB package is suitable only for chips having a low number of leads. In fact, the package is not rigid unless the leads themselves are rigid. Yet rigidity is an essential condition for a package, to avoid any breakage or damage of the chip or one of its leads. The package must be all the more rigid, the greater the surface area of the chip. Increasing the rigidity of the resin cannot be attained without increasing the cross section of the leads. This is possible only with a low density of the leads. Accordingly, this package is not suitable for VLSI chips.